This invention relates to the field of semiconductor technology and, more particularly, to the field of shallow trench isolation.
As the dimensions and feature sizes of semiconductor devices become increasingly smaller, the electrical isolation of individual devices on a chip becomes progressively more challenging. Each device on an integrated circuit chip must be electrically isolated from neighboring devices in order to enable the independent operation of the device and to prevent short-circuiting.
One of the most widely used techniques for the isolation of semiconductor devices is known as shallow trench isolation (STI). The typical steps involved in the fabrication of an STI structure in a semiconductor substrate are illustrated in FIGS. 1-4. The semiconductor substrate 2 shown in FIG. 1 is made by forming a pad (or buffer) oxide layer 4 over a silicon layer 6. A nitride layer 8 is then deposited over the pad oxide layer 4. A photoresist layer 10 is then deposited over nitride layer 8 and patterned using photolithography to create a soft mask opening 12. The nitride layer 8 and oxide layer 4 are successively etched through soft mask opening 12 to create an opening 14, as shown in FIG. 2. Silicon layer 6 is then etched through opening 14 to form a shallow trench 16. In general, etching of the nitride layer 8, pad oxide layer 4, and silicon layer 6 is desirably achieved by anisotropic etching, such that the sidewalls of the trench formed are vertical. Photoresist 10 is removed and the trench 16 is oxidized to produce a liner oxide 15. Trench 16 is then filled with a dielectric material 17 (e.g., an oxide) to provide the structure shown in FIG. 3. Chemical mechanical polishing (CMP) of this structure and removal of nitride layer 8 and pad oxide layer 4 completes the process, and provides the shallow trench isolation structure 18 shown in FIG. 4.
While STI technology has proven to be a highly effective isolation technique-one that avoids the undesirable Bird's Beak formation encountered in other isolation methodologies, such as localized oxidation of silicon (LOCOS)—the performance characteristics of devices created by STI etching can be adversely affected by the presence of sharp top corners 20 on the trench 16. Sharp top corners 20 may result in junction leakage currents, lowered threshold voltages, and unwanted increases in sub-threshold currents when the field effect transistors (FETs) are activated.
A significant problem resulting from the exposure of the top corners of shallow trench isolation structures to wet clean chemistries is shown in FIG. 5. The filling oxide layer 17 in the vicinity of the sharp top corners 20 recedes to form a dip 21, which contributes to the leakage current of MOSFETs and a reduction in threshold voltages.
The effect of STI trench corner sharpness on the threshold voltage of narrow transistors is known as the “Inverse Narrow Width Effect” (INWE). Several strategies have been developed for counteracting or reducing the INWE, including adding a masked boron or BF2 implant into the core of the memory to raise the threshold voltage of the narrow transistors in the core. However, such a doping method is undesirable in that it adds at least two steps to the processing without substantially compensating for the INWE. Alternatively, techniques for increasing STI corner rounding have been developed, including high temperature (i.e., ca. 1100° C.) liner oxidation, liner oxidation in a chlorine ambient, HF undercut of the pad oxide prior to liner oxidation, and high temperature (i.e., ca. 1100° C.) oxidation after CMP. However, each of these techniques suffers from at least one drawback. For example, corner rounding by modification of the etch typically necessitates the use of a new tool, whereas modifications of the oxidation involving very high temperatures may result in increased stress under the nitride layer which in turn may cause dislocations in the active silicon area beneath it.
U.S. Pat. No. 6,265,317 to Chiu et al. describes a process for top corner rounding in an STI structure that involves the selective etching of the nitride layer with a hot phosphoric acid wet etch chemistry. This process results in pull back of the nitride layer from the trench rim. However, in addition to adding a step to the processing, this method is undesirable in that it employs phosphoric acid, which can result in phosphorous contamination of the trench walls at a sensitive stage in the processing.
The present invention is directed to providing shallow trench isolation structures having desirable structural profiles (e.g., rounded top corners) in a simplified and improved manner.